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M95128 M95128-W M95128-R
128 Kbit serial SPI bus EEPROM with high speed clock
Features

Compatible with SPI bus serial interface (positive clock SPI modes) Single supply voltage: - 4.5 to 5.5 V for M95128 - 2.5 to 5.5 V for M95128-W - 1.8 to 5.5 V for M95128-R High speed - 10 MHz clock rate, 5 ms write time Status Register Hardware protection of the Status Register Byte and Page Write (up to 64 bytes) Self-timed programming cycle Adjustable size read-only EEPROM area Enhanced ESD protection More than 1 000 000 write cycles More than 40-year data retention Packages - ECOPACK2(R) (RoHS compliant and Halogen-free)
UFDFPN8 (MB) 2 x 3 mm TSSOP8 (DW) 169 mil width
SO8 (MN) 150 mil width

March 2010
Doc ID 5798 Rev 13
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www.st.com 1
Contents
M95128, M95128-W, M95128-R
Contents
1 2 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8.1 3.8.2 3.8.3 3.8.4 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 4.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 5.2 5.3 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.1 5.3.2 5.3.3 5.3.4 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 5.5
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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5.6
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.6.1 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . 22
6 7
Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8 9 10 11 12
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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List of tables
M95128, M95128-W, M95128-R
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating conditions (M95128) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions (M95128-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions (M95128-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M95128, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M95128-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics (M95128-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics (M95128-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 AC characteristics (M95128, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AC characteristics (M95128-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AC characteristics (M95128-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC characteristics (M95128-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SO8N - 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TSSOP8 - 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 37 UFDFPN8, 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Available M95128x products (package, voltage range, temperature grade) . . . . . . . . . . . 40 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SO, UFDFPN and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SO8N - 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 36 TSSOP8 - 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 37 UFDFPN8, 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline . . . . . . 38
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Description
M95128, M95128-W, M95128-R
1
Description
The M95128, M95128-W and M95128-R are electrically erasable programmable memory (EEPROM) devices accessed by a high speed SPI-compatible bus. The memory array is organized as 16384 x 8 bits. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 1. The device is selected when Chip Select (S) is taken low. Communications with the device can be interrupted using Hold (HOLD). Figure 1. Logic diagram
VCC
D C S W HOLD M95128
Q
VSS
AI12805
Figure 2.
SO, UFDFPN and TSSOP connections
M95128 S Q W VSS 1 2 3 4 8 7 6 5 VCC HOLD C D
AI12806
1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.
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M95128, M95128-W, M95128-R Table 1. Signal names
Signal name C D Q S W HOLD VCC VSS Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect Hold Supply voltage Ground Input Input Output Input Input Input
Description
Direction
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Memory organization
M95128, M95128-W, M95128-R
2
Memory organization
The memory is organized as shown in Figure 3. Figure 3.
HOLD W S C D Q Control Logic
Block diagram
High Voltage Generator
I/O Shift Register
Address Register and Counter
Data Register Status Register
Size of the Read only EEPROM area
Y Decoder
1 Page
X Decoder
AI01272C
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Signal description
3
Signal description
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.
3.1
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
3.2
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C).
3.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
3.4
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
3.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
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Signal description
M95128, M95128-W, M95128-R
3.6
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write instructions.
3.7
VSS ground
VSS is the reference for the VCC supply voltage.
3.8
3.8.1
Supply voltage (VCC)
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 7, Table 8 and Table 9). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
3.8.2
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the internal reset threshold voltage (this threshold is defined in DC tables 12, 13, 14 and 15 as VRES. When VCC passes over the POR threshold, the device is reset and in the following state:

in Standby Power mode deselected (note that, to be executed, an instruction must be preceded by a falling edge on Chip Select (S)) Status register values: - - - the Write Enable Latch (WEL) bit is reset to 0 the Write In Progress (WIP) bit is reset to 0 the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode. The device must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 7, Table 8 and Table 9.
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Signal description
3.8.3
Power-up conditions
When the power supply is turned on, VCC continuously rises from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 12). In addition, the Chip Select (S) input offers a built-in safety feature, as it is edge-sensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must have been high, prior to going low to start the first operation. The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 7, Table 8 and Table 9 and the rise time must not vary faster than 1 V/s.
3.8.4
Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum VCC operating voltage defined in Table 7, Table 8 and Table 9), the device must be:

deselected (Chip Select S should be allowed to follow the voltage applied on VCC) in Standby Power mode (there should not be any internal write cycle in progress).
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Operating features
M95128, M95128-W, M95128-R
4
4.1
Operating features
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To enter the Hold condition, the device must be selected, with Chip Select (S) low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as Serial Clock (C) already being low (as shown in Figure 4). The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as Serial Clock (C) already being low. Figure 4 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. Figure 4. Hold condition activation
C
HOLD
Hold Condition
Hold Condition
AI02029D
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Operating features
4.2
Status Register
Figure 3 shows the position of the Status Register in the control logic of the device. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. For a detailed description of the Status Register bits, see Section 5.3: Read Status Register (RDSR).
4.3
Data Protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if memory bytes are corrupted. Consequently, the device features the following data protection mechanisms:

Write and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - - - - Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Write (WRITE) instruction completion

The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be configured as read-only. The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits of the Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence:
The `last bit of the instruction' can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions). The `next rising edge of Serial Clock (C)' might (or might not) be the next bus transaction for some other device on the SPI bus. Write-protected block size
Array addresses protected Protected block BP1 0 0 1 1 BP0 0 1 0 1 none Upper quarter Upper half Whole memory M95128, M95128-W, M95128-R none 3000h - 3FFFh 2000h - 3FFFh 0000h - 3FFFh
Table 2.
Status Register bits
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Instructions
M95128, M95128-W, M95128-R
5
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3. If an invalid instruction is sent (one not contained in Table 3), the device automatically deselects itself. Table 3. Instruction set
Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array Instruction format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010
Instruction WREN WRDI RDSR WRSR READ WRITE
5.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 5, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high. Figure 5. Write Enable (WREN) sequence
S 0 C Instruction D High Impedance Q
AI02281E
1
2
3
4
5
6
7
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Instructions
5.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 6, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion. Write Disable (WRDI) sequence
S 0 C Instruction D High Impedance Q
AI03750D
Figure 6.
1
2
3
4
5
6
7
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Instructions
M95128, M95128-W, M95128-R
5.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 7. The status and control bits of the Status Register are as follows:
5.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
5.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write or Write Status Register instruction is accepted.
5.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 4) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
5.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Table 4.
b7 SRWD 0 0 0 BP1 BP0 WEL
Status Register format
b0 WIP
Status Register Write Protect Block Protect bits Write Enable Latch bit Write In Progress bit
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Doc ID 5798 Rev 13
M95128, M95128-W, M95128-R Figure 7.
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 Status Register Out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instructions
Read Status Register (RDSR) sequence
0
7
AI02031E
Doc ID 5798 Rev 13
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Instructions
M95128, M95128-W, M95128-R
5.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low, sending the instruction code followed by the data byte on Serial Data input (D), and driving the Chip Select (S) signal high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the selftimed write cycle that takes tW to complete (as specified in Table 16, Table 17, Table 19 and Table 19). The instruction sequence is shown in Figure 8. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write cycle tW, and, 0 when the write cycle is complete. The WEL bit (Write enable latch) is also reset at the end of the write cycle tW. The Write Status Register (WRSR) instruction allows the user to change the values of the BP1, BP0 and SRWD bits:

The Block protect (BP1, BP0) bits define the size of the area that is to be treated as read only, as defined in Table 5. The SRWD bit (Status register write disable bit), in accordance with the signal read on the Write protect pin (W), allows the user to set or reset the write protection mode of the Status Register itself, as shown in Table 5. When in the Write-protected mode, the Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction, including the tW write cycle. The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1 and b0 bits in the Status Register. Bits b6, b5, b4 are always read as 0. Table 5.
W signal 1 0
Protection modes
SRWD bit 0 0 Mode Write protection of the Status Register Memory content Protected area(1) Unprotected area(1)
1
1
Status Register is Writable (if the WREN Software instruction has set the Protected WEL bit) (SPM) The values in the BP1 and BP0 bits can be changed Status Register is Hardware Hardware write protected Protected The values in the BP1 (HPM) and BP0 bits cannot be changed
Write Protected
Ready to accept Write instructions
0
1
Write Protected
Ready to accept Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 5.
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M95128, M95128-W, M95128-R The protection features of the device are summarized in Table 2.
Instructions
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of whether Write Protect (W) is driven high or low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W):
If Write Protect (W) is driven high, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W) is driven low, it is not possible to write to the Status Register even if the Write enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution.) As a consequence, all the data bytes in the memory area that are software-protected (SPM) by the Block protect (BP1, BP0) bits in the Status Register, are also hardware-protected against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be entered:

by setting the Status register write disable (SRWD) bit after driving Write Protect (W) low or by driving Write Protect (W) low after setting the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware-protected mode (HPM) once entered is to pull Write Protect (W) high. If Write Protect (W) is permanently tied high, the Hardware-protected mode (HPM) can never be activated, and only the Software-protected mode (SPM), using the Block protect (BP1, BP0) bits in the Status Register, can be used. Figure 8. Write Status Register (WRSR) sequence
S 0 C Instruction Status Register In 7 High Impedance Q
AI02282D
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
D
6
5
4
3
2
1
0
MSB
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Instructions
M95128, M95128-W, M95128-R
5.5
Read from Memory Array (READ)
As shown in Figure 9, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). If Chip Select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a write cycle is currently in progress. Figure 9.
S 0 C Instruction 16-Bit Address 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
Read from Memory Array (READ) sequence
D High Impedance Q
15 14 13 MSB
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
MSB
AI01793D
1. The most significant address bits (b15, b14) are Don't Care.
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M95128, M95128-W, M95128-R
Instructions
5.6
Write to Memory Array (WRITE)
As shown in Figure 10, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data. The self-timed write cycle, triggered by the rising edge of Chip Select (S), continues for a period tWC (as specified in Table 16 to Table 19.), at the end of which the Write in Progress (WIP) bit is reset to 0. In the case of Figure 10, Chip Select (S) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. If, though, Chip Select (S) continues to be driven low, as shown in Figure 11., the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these devices is 64 bytes). The instruction is not accepted, and is not executed, under the following conditions:

if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) if a write cycle is already in progress if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in) if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
Note:
The self-timed write cycle tW is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as "0" and a programmed bit is read as "1". Figure 10. Byte Write (WRITE) sequence
S 0 C Instruction 16-Bit Address Data Byte 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D High Impedance Q
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
AI01795D
1. The most significant address bits (b15, b14) are Don't Care.
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Instructions Figure 11. Page Write (WRITE) sequence
S 0 C Instruction 16-Bit Address 1 2 3 4 5 6 7 8 9 10
M95128, M95128-W, M95128-R
20 21 22 23 24 25 26 27 28 29 30 31
Data Byte 1
D
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data Byte 2 Data Byte 3 Data Byte N
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
AI01796D
1. The most significant address bits (b15, b14) are Don't Care.
5.6.1
ECC (error correction code) and write cycling
Most M95128, M95128-W and M95128-R devices offer an ECC (error correction code) logic which compares each 4-byte word with 6 EEPROM bits of ECC (the list of concerned devices is defined in Table 24: Available M95128x products (package, voltage range, temperature grade)). As a result, if a single bit out of 4 bytes of data happens to be erroneous during a read operation, the ECC detects it and replaces it by the correct value. The read reliability is therefore improved by the use of this feature. Note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ECC bits), that is, the addressed byte is cycled together with the three other bytes making up the word. It is therefore recommended to write by packets of 4 bytes in order to benefit from the larger amount of write cycles. The maximum number of write cycles is qualified at 1 Million (1 000 000) write cycles, using a cycling routine that writes to the device by multiples of 4-byte packets.
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M95128, M95128-W, M95128-R
Delivery state
6
Delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
7
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 12. Bus master and memory devices on the SPI bus
VSS VCC R SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK CQD Bus master SPI memory device VCC VSS R CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD R SPI memory device CQD VCC VSS R SPI memory device CQD VCC VSS
AI12304c
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 12 shows an example of three memory devices connected to an MCU, on an SPI bus. Only one memory device is selected at a time, so only one memory device drives the Serial Data Output (Q) line at a time, the other memory devices are high impedance. The pull-up resistor R (represented in Figure 12) ensures that a device is not selected if the bus master leaves the S line in the high impedance state.
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Connecting to the SPI bus
M95128, M95128-W, M95128-R
In applications where the bus master might enter a state where all inputs/outputs SPI bus would be in high impedance at the same time (for example, if the bus master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled high): this will ensure that S and C do not become high at the same time, and so, that the tSHCH requirement is met. The typical value of R is 100 k.
7.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 13, is the clock polarity when the bus master is in Stand-by mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1)
Figure 13. SPI modes supported
CPOL CPHA C
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
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M95128, M95128-W, M95128-R
Maximum rating
8
Maximum rating
Stressing the device outside the ratings listed in Table 6 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6.
Symbol TA TSTG TLEAD VO VI IOL IOH VCC VESD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature Lead temperature during soldering Output voltage Input voltage DC output current (Q = 0) DC output current (Q = 1) Supply voltage Electrostatic discharge voltage (human body model)(2) -0.50 -4000 Min. -40 -65 See -0.50 -0.50 Max. 130 150 note (1) VCC+0.6 6.5 5 -5 6.5 4000 Unit C C C V V mA mA V V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100 p F, R1 = 1500 , R2 = 500 ).
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DC and AC parameters
M95128, M95128-W, M95128-R
9
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 7.
Symbol VCC TA Supply voltage Ambient operating temperature (device grade 3)
Operating conditions (M95128)
Parameter Min. 4.5 -40 Max. 5.5 125 Unit V C
Table 8.
Symbol VCC TA
Operating conditions (M95128-W)
Parameter Supply voltage Ambient operating temperature (device grade 6) Ambient operating temperature (device grade 3) Min. 2.5 -40 -40 Max. 5.5 85 125 Unit V C C
Table 9.
Symbol VCC TA
Operating conditions (M95128-R)
Parameter Supply voltage Ambient operating temperature Min. 1.8 -40 Max. 5.5 85 Unit V C
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M95128, M95128-W, M95128-R Table 10.
Symbol CL Load capacitance Input rise and fall times Input pulse voltages Input and output(1) timing reference voltages
1. Output Hi-Z is defined as the point where data out is no longer driven.
DC and AC parameters
AC measurement conditions
Parameter Min. 100 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
Figure 14. AC measurement I/O waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
Table 11.
Symbol COUT CIN
Capacitance(1)
Parameter Output capacitance (Q) Input capacitance (D) Input capacitance (other pins) Test condition VOUT = 0 V VIN = 0 V VIN = 0 V Min. 8 8 6 Max. pF pF pF Unit
1. Sampled only, not 100% tested, at TA =25 C and a frequency of 5 MHz.
Table 12.
Symbol ILI ILO
DC characteristics (M95128, device grade 3)
Parameter Input leakage current Output leakage current Test condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5 MHz, VCC = 5 V, Q = open C = 0.1VCC/0.9VCC at 10 MHz, VCC = 5 V, Q = open Supply current (Standby Power mode) Input low voltage Input high voltage Output low voltage Output high voltage Internal reset threshold voltage IOL = 2 mA, VCC = 5 V IOH = -2 mA, VCC = 5 V 0.8 VCC 2.5 4.0 S = VCC, VCC = 5 V, VIN = VSS or VCC -0.45 0.7 VCC Min. Max. 2 2 4 8 5 0.3 VCC VCC+1 0.4 Unit A A mA mA A V V V V V
ICC
Supply current
ICC1 VIL VIH VOL
(1)
VOH(1) VRES(2)
1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
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DC and AC parameters
M95128, M95128-W, M95128-R
2. Characterized only, not 100% tested.
Table 13.
Symbol ILI ILO
DC characteristics (M95128-W, device grade 6)
Parameter Input leakage current Output leakage current Test condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5 MHz, VCC = 2.5 V, Q = open C = 0.1VCC/0.9VCC at 5 MHz, VCC = 5 V, Q = open Supply current (Write) Supply current (Standby Power mode) Input low voltage Input high voltage Output low voltage Output high voltage Internal reset threshold voltage VCC = 2.5 V and IOL = 1.5 mA or VCC = 5 V and IOL = 2 mA VCC = 2.5 V and IOH = -0.4 mA or VCC 0.8 VCC = 5 V and IOH = -2 mA 1.0 1.65 During tW, S = VCC, 2.5 V < VCC < 5.5 V S = VCC, VIN = VSS or VCC, 2.5 V < VCC < 5.5 V -0.45 0.7 VCC Min. Max. 2 2 3 5 5 5 0.3 VCC VCC+1 0.4 Unit A A mA mA mA A V V V V V
ICC
Supply current (Read)
ICC0(1) ICC1 VIL VIH VOL VOH VRES(2)
1. Characterized value, not tested in production. 2. Characterized only, not 100% tested.
Table 14.
Symbol ILI ILO ICC ICC0(1) ICC1 VIL VIH VOL
DC characteristics (M95128-W, device grade 3)
Parameter Input leakage current Output leakage current Supply current (Read) Supply current (Write) Supply current (Standby Power mode) Input low voltage Input high voltage Output low voltage VCC = 2.5 V and IOL = 1.5 mA or VCC = 5 V and IOL = 2 mA Test condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5 MHz, VCC = 2.5 V, Q = open During tW, S = VCC, 2.5 V < VCC < 5.5 V S = VCC, VIN = VSS or VCC 2.5 V < VCC < 5.5 V, -0.45 0.7 VCC Min. Max. 2 2 3 6 5 0.3 VCC VCC+1 0.4 Unit A A mA mA A V V V
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M95128, M95128-W, M95128-R Table 14.
Symbol VOH VRES(2)
DC and AC parameters
DC characteristics (M95128-W, device grade 3)
Parameter Output high voltage Internal reset threshold voltage Test condition Min. Max. Unit V 1.65 V
VCC = 2.5 V and IOH = -0.4 mA or 0.8 VCC VCC = 5 V and IOH = -2 mA 1.0
1. Characterized value, not tested in production. 2. Characterized only, not 100% tested.
Table 15.
Symbol ILI ILO
DC characteristics (M95128-R)
Parameter Input leakage current Output leakage current Test condition(1) VIN = VSS or VCC S = VCC, voltage applied on Q = VSS or VCC VCC = 1.8 V, C = 0.1 VCC or 0.9VCC, fC = 2 MHz, Q = open VCC = 2.5 V, C = 0.1 VCC or 0.9VCC, fC = 2 MHz, Q = open VCC = 5.0 V, S = VCC, VIN = VSS or VCC Min. Max. 2 2 1 3 5 3 3 -0.45 -0.45 0.7VCC 0.75VCC 0.3VCC 0.25VCC VCC+1 VCC+1 0.2VCC 0.3 0.8VCC Unit A A mA mA A A A V V V V V V V
ICCR
Supply current (Read)
ICC1
Supply current (Standby)
VCC = 2.5 V, S = VCC, VIN = VSS or VCC VCC = 1.8 V, S = VCC, VIN = VSS or VCC
VIL
Input low voltage
2.5V < VCC < 5.5V 1.8V < VCC < 2.5V
VIH
Input high voltage
2.5V < VCC < 5.5V 1.8V < VCC < 2.5V
VOL
Output low voltage
VCC = 2.5 V, IOL = 1.5 mA or VCC = 5.5 V, IOL = 2 mA VCC = 1.8 V, IOL = 0.15 mA
VOH VRES(2)
Output high voltage Internal reset threshold voltage
VCC = 2.5 V, IOH = -0.4 mA, or VCC = 5.5 V, IOH = -2 mA, or VCC = 1.8 V, IOH = -0.1 mA
1.0
1.65
V
1. If the application uses the M95128-R device with 2.5 V < VCC < 5.5 V and -40 C < TA < +85 C, please refer to Table 17: AC characteristics (M95128-W, device grade 6) instead of the above table. 2. Characterized only, not 100% tested.
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DC and AC parameters Table 16.
M95128, M95128-W, M95128-R AC characteristics (M95128, device grade 3)
Test conditions specified in Table 10 and Table 7
Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH (1) tCL
(1) (2) (2)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency
Parameter
Min. D.C. 30 30 40 30 30 45 45
Max. 10
Unit MHz ns ns ns ns ns ns ns
S active setup time S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low setup time before HOLD active Clock low setup time before HOLD not active
tCLCH tCHCL
2 2 10 10 30 30 0 0 40 40 0 40 40 40 40 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time
tCLQV tCLQX tQLQH tQHQL
(2) (2)
tHHQV tHLQZ (2) tW
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production.
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M95128, M95128-W, M95128-R Table 17. AC characteristics (M95128-W, device grade 6)
DC and AC parameters
Test conditions specified in Table 10 and Table 8 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH (1) tCL
(1) (2) (2)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency S active setup time
Parameter
Min. D.C. 90 90 100 90 90 90 90
Max. 5
Unit MHz ns ns ns ns ns ns ns
S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low setup time before HOLD active Clock low setup time before HOLD not active
tCLCH tCHCL
1 1 20 30 70 40 0 0 100 60 0 50 50 50 100 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time
tCLQV tCLQX tQLQH tQHQL
(2) (2)
tHHQV tHLQZ (2) tW
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production.
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DC and AC parameters Table 18.
M95128, M95128-W, M95128-R AC characteristics (M95128-W, device grade 3)
Test conditions specified in Table 10 and Table 8
Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH (1) tCL
(1) (2) (2)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency S active setup time
Parameter
Min. D.C. 90 90 100 90 90 90 90
Max. 5
Unit MHz ns ns ns ns ns ns ns
S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low setup time before HOLD active Clock low setup time before HOLD not active
tCLCH tCHCL
1 1 20 30 70 40 0 0 100 60 0 50 50 50 100 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time
tCLQV tCLQX tQLQH tQHQL
(2) (2)
tHHQV tHLQZ (2) tW
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 2. Value guaranteed by characterization, not 100% tested in production.
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M95128, M95128-W, M95128-R Table 19. AC characteristics (M95128-R)
DC and AC parameters
Test conditions specified in Table 10 and Table 9(1) Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH (3) tCL
(3) (4) (4)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency
Parameter
Min.(2) D.C. 200 200 200 200 200 200 200
Max.(2) 2
Unit MHz ns ns ns ns ns ns ns
S active setup time S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low setup time before HOLD active Clock low setup time before HOLD not active
tCLCH tCHCL
1 1 40 50 140 90 0 0 250 150 0 100 100 100 250 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(4)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time
tCLQV tCLQX tQLQH tQHQL
(4) (4)
tHHQV tHLQZ (4) tW
1. If the application uses the M95128-R at 2.5 V VCC 5.5 V and -40 C TA +85 C, please refer to Table 17 instead of the above table. 2. This is preliminary data. 3. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max) 4. Value guaranteed by characterization, not 100% tested in production.
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DC and AC parameters Figure 15. Serial input timing
M95128, M95128-W, M95128-R
tSHSL S tCHSL C tDVCH tCHCL tCHDX D MSB IN LSB IN tCL tCLCH tSLCH tCH tCHSH tSHCH
Q
High impedance
AI01447d
Figure 16. Hold timing
S tHLCH tCLHL C tCLHH tHLQZ Q tHHQV tHHCH
HOLD
AI01448c
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M95128, M95128-W, M95128-R Figure 17. Serial output timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D LSB IN
ADDR
DC and AC parameters
tSHSL
tCLCH
tCHCL
tCL
tSHQZ
AI01449f
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Package mechanical data
M95128, M95128-W, M95128-R
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 18. SO8N - 8-lead plastic small outline, 150 mils body width, package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 20.
SO8N - 8-lead plastic small outline, 150 mils body width, package mechanical data
millimeters inches(1) Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 - 0.25 0 0.40 1.04 5.00 6.20 4.00 - 0.50 8 1.27 0.0409 0.1929 0.2362 0.1535 0.05 0.189 0.2283 0.1496 0.0098 0 0.0157 0.25 0.0039 0.0492 0.011 0.0067 0.0189 0.0091 0.0039 0.1969 0.2441 0.1575 0.0197 8 0.05 Typ Min Max 0.0689 0.0098
Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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M95128, M95128-W, M95128-R
Package mechanical data
Figure 19. TSSOP8 - 8-lead thin shrink small outline, package outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
1. Drawing is not to scale.
Table 21.
TSSOP8 - 8-lead thin shrink small outline, package mechanical data
millimeters inches(1) Max 1.200 0.050 1.000 0.800 0.190 0.090 0.150 1.050 0.300 0.200 0.100 3.000 0.650 6.400 4.400 0.600 1.000 0 8 8 2.900 - 6.200 4.300 0.450 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ Min Max 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295
Symbol Typ A A1 A2 b c CP D e E E1 L L1 N (number of leads) Min
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
M95128, M95128-W, M95128-R
Figure 20. UFDFPN8, 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline
D L3 e b L1
E
E2
L A D2 ddd A1
UFDFPN-01
1. Drawing is not to scale. 2. The central pad (the area delimited by E2 and D2 in the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 22.
UFDFPN8, 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, mechanical data
millimeters inches(1) Max 0.6 0.05 0.3 2.1 1.7 3.1 0.3 0.5 0.15 0.3 0.0118 0.08 Typ 0.0217 0.0008 0.0098 0.0787 0.063 0.1181 0.0079 0.0197 0.0177 Min 0.0177 0 0.0079 0.0748 0.0591 0.1142 0.0039 0.0157 Max 0.0236 0.002 0.0118 0.0827 0.0669 0.122 0.0118 0.0197 0.0059
Symbol Typ A A1 b D D2 E E2 e L L1 L3 ddd
(2)
Min 0.45 0 0.2 1.9 1.5 2.9 0.1 0.4
0.55 0.02 0.25 2 1.6 3 0.2 0.5 0.45
0.08
1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring.
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M95128, M95128-W, M95128-R
Part numbering
11
Part numbering
Table 23.
Example: Device type M95 = SPI serial access EEPROM Device function 128 = 128 Kbit (16384 x 8) Operating voltage blank = VCC = 4.5 to 5.5 V W = VCC = 2.5 to 5.5 V R = VCC = 1.8 to 5.5 V Package MN = SO8 (150 mils width) DW = TSSOP8 (169 mils width) MB = UFDFPN8 (MLP8 2 x 3 mm) Device grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 3 = Device tested with high reliability certified flow(1) Automotive temperature range (-40 to 125 C) Option blank = Standard packing T = Tape and reel packing Plating technology P or G = ECOPACK2(R) (RoHs compliant and Halogen-free) Process(2) /P or /PC = DP26% Chartered
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a co. 2. The Process letter /P applies only to Grade 3 devices.
Ordering information scheme
M95128 - W MN 6 T P /P
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.
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Part numbering Table 24.
M95128, M95128-W, M95128-R Available M95128x products (package, voltage range, temperature grade)
M95128-R (1.8 V to 5.5 V) Grade 6 Grade 6 Grade 6 M95128-W (2.5 V to 5.5 V) Grade 6 Grade 3(1) Grade 3(1) M95128 (4.5 V to 5.5 V) Grade 3(1) -
Package
SO8N (MN) UFDFPN8 (MLP8) 2 x 3 mm (MB) TSSOP (DW)
1. Grade 3 products (without ECC) are codified as /P and /PC in Table 23: Ordering information scheme).
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M95128, M95128-W, M95128-R
Revision history
12
Revision history
Table 25.
Date 17-Nov-1999 07-Feb-2000 22-Feb-2000 15-Mar-2000 29-Jan-2001
Document revision history
Revision 2.1 2.2 2.3 2.4 2.5 Changes New -V voltage range added (including the tables for DC characteristics, AC characteristics, and ordering information). New -V voltage range extended to M95256 (including AC characteristics, and ordering information). tCLCH and tCHCL, for the M95xxx-V, changed from 1s to 100ns -V voltage range changed to 2.7-3.6V Lead Soldering Temperature in the Absolute Maximum Ratings table amended Illustrations and Package Mechanical data updated Correction to header of Table 12B TSSOP14 Illustrations and Package Mechanical data updated Document promoted from Preliminary Data to Full Data Sheet Announcement made of planned upgrade to 10 MHz clock for the 5V, -40 to 85C, range. M95128 split off to its own datasheet. Data added for new and forthcoming products, including availability of the SO8 narrow package. Omission of SO8 narrow package mechanical data remedied -V voltage range removed Table of contents, and Pb-free options added. -S voltage range extended to -R. VIL(min) improved to -0.45V Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified M95128 datasheet merged back in. Product List summary table added. AEC-Q100-002 compliance. Device Grade information clarified. tHHQX corrected to tHHQV. 10MHz product becomes standard
12-Jun-2001
2.6
08-Feb-2002 09-Aug-2002 24-Feb-2003 26-Jun-2003 21-Nov-2003
2.7 2.8 2.9 2.10 3.0
17-Mar-2004
4.0
21-Oct-2004
5.0
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Revision history Table 25.
Date
M95128, M95128-W, M95128-R Document revision history (continued)
Revision Changes New M95128 datasheet extracted from the M95128/256 datasheet. Order of sections modified. ECC (error correction code) and Write cycling paragraph added. Section 3.8: Supply voltage (VCC) added and information removed below Section 4: Operating features. Power up state removed below Section 6: Delivery state. Figure 13: SPI modes supported modified and Note 2 added. ICC1 specified over the whole VCC range and ICC0 added to Table 13, Table 14 and Table 15. ICC specified over the whole VCC range in Table 13. tCHHL and tCHHH replaced by tCLHL and tCLHH, respectively. Figure 16: Hold timing modified. Process letter and Note 1 added to Table 23: Ordering information scheme. "AC Characteristics (M95128, Device Grade 6)" Table (for 10MHz frequency) removed. Note 1 removed from Table 19: AC characteristics (M95128-R). TA added to Table 6: Absolute maximum ratings. PDIP8 (BN) and SO8 wide (MW) packages removed. M95128-W and M95128-R are no longer under development. Test conditions changed for VOL and VOH in Section Table 14.: DC characteristics (M95128-W, device grade 3). Figure 12: Bus master and memory devices on the SPI bus modified. SO8N package specifications updated (see Table 20 and Figure 18). V Process specified and A Process replaced by P in Table 23: Ordering information scheme. Section 3.8: Supply voltage (VCC), Section 4.3: Data Protection and protocol control, Section 5.4: Write Status Register (WRSR), Section 5.6: Write to Memory Array (WRITE) and Section 5.6.1: ECC (error correction code) and Write cycling updated. Note removed below Figure 12: Bus master and memory devices on the SPI bus, replaced by paragraph. Test conditions modified for ICC1 and ICC0 in Table 15: DC characteristics (M95128-R). AC characteristics values added for fC frequency = 10 MHz in Table 16: AC characteristics (M95128, device grade 3). tW modified in Table 19: AC characteristics (M95128-R). Section 10: Package mechanical data: - UFDFPN8 package added - Package mechanical inch values calculated from mm and rounded to 4 decimal digits Table 24: Available M95128x products (package, voltage range, temperature grade) added. Blank removed below Plating technology, first note removed, process A added and process V removed in Table 23: Ordering information scheme. Section 3.7: VSS ground added. Section 3.8.2: Device reset, Section 3.8.4: Power-down and Section 5.6.1: ECC (error correction code) and Write cycling modified. VIL and VIH modified in Table 15: DC characteristics (M95128-R). Table 24: Available M95128x products (package, voltage range, temperature grade) updated.
13-Apr-2006
6
27-Jun-2006
7
04-Oct-2007
8
15-Jan-2008
9
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M95128, M95128-W, M95128-R Table 25.
Date
Revision history
Document revision history (continued)
Revision Changes M95128, device grade 3 devices is now offered at 10 MHz frequency. Section 3.8: Supply voltage (VCC) on page 10 and Section 5.4: Write Status Register (WRSR) on page 18 updated. Table 15: DC characteristics (M95128-R) on page 29 modified. tCH and tCL modified in Table 16: AC characteristics (M95128, device grade 3) on page 30. Figure 15: Serial input timing, Figure 16: Hold timing and Figure 17: Serial output timing modified. Process A removed from Table 23: Ordering information scheme. Small text changes. Section 3.8: Supply voltage (VCC) and Section 5.4: Write Status Register (WRSR) updated. Note added to Section 5.6: Write to Memory Array (WRITE). ICC modified in Table 12: DC characteristics (M95128, device grade 3). VRES added to DC characteristics tables 12, 13, 14 and 15. Note added to Table 19: AC characteristics (M95128-R). Note added below Figure 20: UFDFPN8, 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline. Small text changes. Section 5.6.1: ECC (error correction code) and write cycling modified (applies to all devices). TLEAD, IOL and IOH added to Table 6: Absolute maximum ratings. Note added to Table 15: DC characteristics (M95128-R). Process modified in Table 23: Ordering information scheme. All packages are ECOPACK2 compliant. Section 5.6.1: ECC (error correction code) and write cycling and Table 24: Available M95128x products (package, voltage range, temperature grade) updated.
11-Jul-2008
10
17-Feb-2009
11
12-Jan-2010
12
02-Mar-2010
13
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M95128, M95128-W, M95128-R
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